The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Memory in a cellular phone or a computer system may be arranged in a memory hierarchy, which includes memory devices of different speeds, types and sizes. The type, size and proximity of a memory device to a processor affect speed of that memory device. Due to costs of memory and limited space near the processor, a memory hierarchy may be organized into several levels.
Many processors use and/or have memory caches to store copies of highly used data and instructions in order to improve access speed and overall processing speed. A memory cache, such as an instruction (I)-cache, is a portion of memory that may include high-speed static random access memory (SRAM). SRAM is included instead of slower dynamic RAM (DRAM), which is commonly used for a main memory. The memory cache may be referred to as a cache store or RAM (Random Access Memory) cache. Memory caches may be included at the highest level of memory and on the same integrated circuit (IC) as the processor. Such internal memory caches are also referred to as local or Level 1 (L1) caches.
A memory cache includes an array of cells. Each cell stores a bit of information. An instruction, which may include, for example, 4-8 bits is stored and accessed through a read cycle. To access a word of instructions multiple read cycles are executed. During each read cycle, cells associated with an instruction are accessed by toggling both a row path (word line) and multiple column paths (bit lines) of the array for that word. The toggling of row and column paths includes tasks such as decoding row and column addresses, generating a word line signal, precharging bit lines, sensing-amplification, and latching data. Sensing-amplification refers to the detection and amplification of stored bit information. A significant amount of energy is associated with the stated tasks.